1. Field of the Invention
The present invention relates to semiconductor manufacturing in general, and more specifically to methods for forming low leakage current borderless contact.
2. Description of the Prior Art
The major objectives of the semiconductor industry have been to continually increase the device and circuit performances of silicon chips, while maintaining or even decreasing the cost of producing these same silicon chips. These objectives have been successfully addressed by the ability of the semiconductor industry to fabricate silicon devices, with sub-micron features. The ability to use sub-micron features, or micro-miniaturization, has allowed performance improvements to be realized by the reduction of resistances and parasitic capacitances, resulting from the use of smaller features. In addition, the use of sub-micron features results in smaller silicon chips with increased circuit densities, thus allowing more silicon chips to be obtained from a starting silicon substrate, thus reducing the cost of an individual silicon chip.
The attainment of micro-miniaturization has been basically a result of advances in specific semiconductor fabrication disciplines, such as photolitography and reactive ion etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron features in photoresist layers to be routinely achieved. In addition, similar developments in the dry etching discipline have allowed these sub-micron images in photoresist layers to be successfully transferred to underlying materials, which are used for the creation advanced semiconductor devices. However, the use of sub-micron features can improve silicon device performance and decrease silicon chip coast, but will introduce specific semiconductor fabrication problems and will not encounter with larger featured counterparts. For example, specific designs, which are used to connect and overlying metallization structure to an underlying metallization structure, sometimes require that metal filled via holes in insulator layers, and not always be fully landed. That is the result of the metal filled via not being placed entirely on the underlying metallization structure. The inability of fully land a via on an underlying metal structure, places a burden on the process used to create the via hole. For example if the chip design demands a non-fully landed, or has a borderless contact, the dry etching procedure used to create the via has to be able to insure complete removal of insulator materials from the area where the via landed on the underlying metal structure. Therefore, the dry etching procedure necessitates the use of an overetch cycle.
However, overetching can create problems. FIG. 1A to FIG. 1D are schematic representations of structures at various stages during the formulation of borderless contact using conventional, prior art techniques. A substrate 100 is provided with a source/drain junction 110 formed therein, as shown in FIG. 1A. A shallow trench isolation (STI) 120 is formed beside the junction 110. Then, a silicon nitride layer 140 is deposited on the substrate 100 as a stop layer, as shown in FIG. 1B. A planarized interlevel dielectric layer 150 is subsequently formed over the stop layer 140. The formulation of contact includes two etching steps, i.e.; etching interlevel dielectric layer 150 is the first and etching stop layer 140 is the second. FIG. 1C shows the first step and FIG. 1D shows the second step. While in the second step, the selectivity between silicon nitride and silicon oxide is about 1.5:1. This will make overetching on top surface of STI 120 near bottom of junction 110, and leakage current will occur between side wall of STI 20 and substrate 100 when tungsten or copper plug filling the contact 160, as shown in FIG. 1D.